The FINFET is a promising integrated circuit technology that employs a thin (10 nm–100 nm) vertical member as the source, drain and body of a field effect transistor (FET) and has a gate that is next to two vertical sides and the top of the channel. With such a thin body, there is very strong gate coupling, so that fully depleted operation is readily achieved. These structures will require overvoltage protection from electrical overstress (EOS), such as electrostatic discharge (ESD), as well as other voltage or current related stress events that are present in the semiconductor manufacturing, shipping and test processes. EOS events include over-current stress, latchup, and high current that occurs during testing and stressing. ESD events such as those occurring in the course of the human body model (HBM), machine model (MM), charged device model (CDM), transient latchup (TLU), cable discharge model, cassette model (CM) as well as other events can lead to electrical failure of FINFET structures.
Hence, it is evident that EOS and ESD protection of FINFET structures are necessary to provide adequate ESD protection for these structures.
U.S. Pat. No. 6,015,993 illustrates construction techniques for lateral ESD devices having a gated diode, where the channel is formed in bulk silicon or in the device layer of an SOI wafer. This structure is not compatible with FINFET structures and FINFET processing.